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a
Adjustable Output Ultralow IQ, 200 mA, SOT-23, anyCAP Low Dropout Regulator ADP3331
(R)
FUNCTIONAL BLOCK DIAGRAM
Q1 THERMAL PROTECTION ERR Q2 SD DRIVER gm IN OUT
FEATURES High Accuracy over Line and Load: 0.7% @ 25 C, 1.4% over Temperature Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA Can Be Used as a High Current (>1 A) LDO Controller Requires Only CO = 0.47 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: 10 nA Typical 2.6 V to 12 V Supply Range 1.5 V to 11.75 V Output Range -40 C to +85 C Ambient Temperature Range Ultrasmall Thermally Enhanced Chip-on-LeadTM SOT-23-6 Lead Package APPLICATIONS Cellular Telephones Notebook, Palmtop Computers Battery-Powered Systems PCMCIA Regulators Bar Code Scanners Camcorders, Cameras
ADP3331
CC FB
BAND GAP REF
GND
ERR
ADP3331
OUT VIN C1 + 0.47 F IN SD
6
R3 330k R1 +
EOUT VOUT C2 0.47 F
FB GND
4
R2
ON OFF
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3331 is a member of the ADP330x family of precision low dropout anyCAP voltage regulators. The ADP3331 operates with an input voltage range of 2.6 V to 12 V and delivers a load current up to 200 mA. The ADP3331 stands out from the conventional LDOs with a novel architecture and an enhanced process that enables it to offer performance advantages and higher output current than its competition. Its patented design requires only a 0.47 mF output capacitor for stability. This device is insensitive to capacitor equivalent series resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types
for space restricted applications. The ADP3331 achieves exceptional accuracy of 0.7% at room temperature and 1.4% overall accuracy over temperature, line, and load variations. The dropout voltage of the ADP3331 is only 140 mV (typical) at 200 mA. This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 2 mA. The ADP3331 has ultralow quiescent current 34 mA (typical) in light load situations. The SOT-23-6 package has been thermally enhanced using Analog Device's proprietary Chip-on-Lead feature to maximize power dissipation.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADP3331-SPECIFICATIONS noted.)
Parameter OUTPUT VOLTAGE ACCURACY HIGH OUTPUT VOLTAGE RANGE
3
(TA = -40 C to +85 C, VIN = 7 V, CIN = 0.47 F, COUT = 0.47 F, unless otherwise
1, 2
Symbol
Conditions VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM 2.35 V, IL = 0.1 mA to 200 mA, TA = 25C VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM 2.35 V, IL = 0.1 mA to 150 mA, TA = -40C to +85C VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM 2.35 V, IL = 0.1 mA to 200 mA, TA = -20C to +85C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 200 mA, TA = 25C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 150 mA, TA = -40C to +85C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 200 mA, TA = -20C to +85C
Min
Typ
Max
Unit
-0.7
+0.7
%
-1.4
+1.4
%
-1.4
+1.4
%
OUTPUT VOLTAGE ACCURACY LOW OUTPUT VOLTAGE RANGE
3
-0.7
+0.7
%
-1.4
+1.4
%
-1.4 0.06 0.04 1.6 1.2 0.4 34 37 0.14 0.11 0.042 0.025 300 47 95 2.0
+1.4
% mV/V mV/mA
LINE REGULATION LOAD REGULATION GROUND CURRENT
DVO DVIN DVO DIL IGND
VIN = VOUTNOM + 0.25 V to 12 V TA = 25C IL= 0.1 mA to 200 mA TA = 25C IL = 200 mA, TA = -20C to +85C IL = 150 mA IL = 50 mA IL = 0.1 mA VIN = VOUTNOM - 100 mV IL = 0.1 mA VOUT = 98% of VOUTNOM IL = 200 mA, TA = -20C to +85C IL = 150 mA IL = 10 mA IL = 1 mA VIN = VOUTNOM + 1 V f = 10 Hz-100 kHz, CL = 10 mF IL = 200 mA, CNR = 10 nF, VOUT = 3 V f = 10 Hz-100 kHz, CL = 10 mF IL = 200 mA, CNR = 0 nF, VOUT = 3 V ON OFF 0 < SD 12 V 0 < SD 5 V SD = 0 V, VIN = 12 V
4.0 3.1 1.1 50 55 0.23 0.17 0.06 0.05
mA mA mA mA mA V V V V mA mV rms mV rms
GROUND CURRENT IN DROPOUT DROPOUT VOLTAGE
2
IGND VDROP
PEAK LOAD CURRENT OUTPUT NOISE
ILDPK VNOISE
SHUTDOWN THRESHOLD SHUTDOWN PIN INPUT CURRENT GROUND CURRENT IN SHUTDOWN MODE
VTHSD ISD
0.4 1.9 1.4 0.01 9 6 2
V V mA mA mA
IGNDSD
-2-
REV. A
ADP3331
Parameter OUTPUT CURRENT IN SHUTDOWN MODE ERROR PIN OUTPUT LEAKAGE ERROR PIN OUTPUT LOW VOLTAGE Symbol IOSD IEL VEOL Conditions TA = 25C @ VIN = 12 V TA = 85C @ VIN = 12 V VEO = 5 V ISINK = 400 mA 0.19 Min Typ Max 1 2 1 0.40 Unit mA mA mA V
NOTES 1 Ambient temperature of 85C corresponds to a junction temperature of 125C under typical full load test conditions. 2 Application stable with no load. 3 Assumes the use of ideal resistors. Overall accuracy also depends on the tolerance of the external resistors used to set the output voltage. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . . -0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . -40C to +85C Operating Junction Temperature Range . . . -40C to +125C qJA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . 165C/W qJA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . 190C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
OUT IN
1 2
ADP3331
6
SD
5 FB TOP VIEW ERR 3 (Not to Scale) 4 GND
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3
Name OUT IN ERR
Function Output of the Regulator. Bypass to ground with a 0.47 mF or larger capacitor. Regulator Input. Open Collector Output that goes low to indicate that the output is about to go out of regulation. Ground. Feedback Input. Connect to an external resistor divider, which sets the output voltage. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin.
ORDERING GUIDE
4 5 Branding L9B 6
GND FB
Model ADP3331ART
Output Voltage ADJ
Package Option RT-6 (SOT-23-6)
SD
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3331 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADP3331-Typical Performance Characteristics
3.010 3.008 3.006
VOUT = 3.0V
3.005 3.004 3.003
OUTPUT VOLTAGE (V)
45
VOUT = 3.0V VIN = 7V
VOUT = 3V 40
GROUND CURRENT ( A)
IL = 100 A
OUTPUT VOLTAGE (V)
3.004 3.002 3.000 2.998 2.996 2.994 2.992
IL = 0mA
35 30 25 20 15 10 5 0 IL = 0 A
3.002 3.001 3.000 2.999 2.998 2.997 2.996 2.995
IL = 10mA
IL = 50mA
IL = 100mA
IL = 200mA
IL = 150mA
2.990 3.25 4
5
6 7 8 9 10 INPUT VOLTAGE (V)
11
12
2.994 0 25 50 75 100 125 150 175 200 OUTPUT LOAD (mA)
0
2
4 6 8 INPUT VOLTAGE (V)
10
12
TPC 1. Line Regulation Output Voltage vs. Supply Voltage
TPC 2. Output Voltage vs. Load Current
TPC 3. Ground Current vs. Supply Voltage
1.6 VIN = 7V 1.4
0.4 IL = 0mA
GROUND CURRENT (mA)
GROUND CURRENT (mA)
0.3
1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 OUTPUT LOAD (mA) 200
OUTPUT VOLTAGE (%)
IL = 50mA
0.2 IL = 150mA 0.1 IL = 200mA 0.0
-0.1 -45 -25
-5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE ( C)
3.0 VIN = 7V 2.8 IL = 200mA 2.6 2.4 2.2 IL = 150mA 2.0 1.8 IL = 100mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 IL = 50mA 0.2 IL = 0mA 0 -45 -25 -5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE ( C)
TPC 4. Ground Current vs. Load Current
TPC 5. Output Voltage Variation % vs. Junction Temperature
TPC 6. Ground Current vs. Junction Temperature
250
3.5 3.0
VOUT = 3V SD = VIN RL = 15
CL = 0.47 F
INPUT/OUTPUT VOLTAGE (mV)
3
VOUT (V)
200
INPUT/OUTPUT VOLTAGE (V)
2.5 2.0 1.5 1.0 0.5 0
2 1 0 10
CL = 10 F
150
VIN = 7V VOUT = 3V SD = VIN RL = 15
100
VIN (V)
5 0
50
0
0
25
50 75 100 125 150 175 200 OUTPUT LOAD (mA)
0
1.0
2.0 3.0 TIME (sec)
4.0
5.0
0
100
200 300 TIME ( s)
400
500
TPC 7. Dropout Voltage vs. Output Current
TPC 8. Power-Up/Power-Down
TPC 9. Power-Up Response
-4-
REV. A
ADP3331
3.100
3.040
VOUT (V)
VOUT (V)
3.040 3.000 2.960 2.920 VOUT = 3V RL = 15 CL = 10 F
V
3.050 3.000 2.950 2.900 200
mA
3.000 2.960 2.920 VOUT = 3V RL = 15 CL = 0.47 F
VIN = 7V VOUT = 3V CL = 0.47 F
VIN (V)
VIN (V)
7.5 7.0 0 100 200 300 TIME ( s) 400 500
7.5 7.0 0 100 200 300 TIME ( s) 400 500
100 20mA 0
0
200
400
600
800
1000
TIME ( s)
TPC 10. Line Transient Response
TPC 11. Line Transient Response
TPC 12. Load Transient Response
3.100
V
3.050
V
3 0 500
VOUT
3 2 VOUT 1
3.000 2.950 2.900 200 VIN = 7V VOUT = 3V CL = 10 F
mA
VIN = 7V VOUT = 3V CL = 10 F RL = 15
400
V
300 200 100
IOUT
0 VERR 3 0 2 VSD 0
mA
100 20mA 0
VIN = 7V
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME (Sec)
0
200
400
600
800
1000
0
200
TIME ( s)
400 600 TIME ( s)
800
1000
TPC 13. Load Transient Response
TPC 14. Short Circuit Current
TPC 15. Turn On-Turn Off Response
0 VOUT = 3.0V -10 RIPPLE REJECTION (dB) -20 -30 -40 -50 -60 -70 -80 -90 10 100 CL = 10 F IL = 200mA CL = 10 F IL = 0.1mA 1k 10k 100k FREQUENCY (Hz) 1M 10M CL = 0.47 F IL = 200mA CL = 0.47 F IL = 0.1mA
160 140
1
CL = 0.47 F CNR = 0
VOLTAGE NOISE SPECTRAL DENSITY ( V/ Hz)
120
RMS NOISE ( V)
IL = 200mA
CL = 10 F CNR = 0
CL = 0.47 F CNR = 10nF
100 80 60 40 20 0 0
IL = 0mA WITH NOISE REDUCTION IL = 0mA IL = 200mA WITH NOISE REDUCTION
0.1
CL = 10 F CNR = 10nF
VOUT = 3.0V IL = 200mA
40 50
10
20 30 CL ( F)
0.01 10
100
1k 10k FREQUENCY (Hz)
100k
1M
TPC 16. Power Supply Ripple Rejection
TPC 17. RMS Noise vs. CL (10 Hz to 100 kHz)
TPC 18. Output Noise Density
REV. A
-5-
ADP3331
THEORY OF OPERATION
The ADP3331 anyCAP LDO uses a single control loop for both regulation and reference functions, as shown in Figure 2. The output voltage is sensed by an external resistive voltage divider consisting of R1 and R2. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier.
INPUT Q1 COMPENSATION CAPACITOR PTAT VOS R4 OUTPUT ATTENUATION (VBANDGAP/VOUT) R3 D1 (a) PTAT CURRENT R1 CLOAD RLOAD R2
innovative design allows the circuit to be stable with just a small 0.47 mF capacitor on the output. Additional advantages of the pole-splitting scheme include superior line noise rejection and very high regulator gain. The high gain leads to excellent regulation, and 1.4% accuracy is guaranteed over line, load, and temperature. Additional features of the circuit include current limit, thermal shutdown, and an error flag. Compared to standard solutions that give a warning after the output has lost regulation, the ADP3331 provides improved system performance by enabling the ERR pin to give a warning just before the device loses regulation. As the chip's temperature rises above +165C, the circuit activates a soft thermal shutdown to reduce the current to a safe level. The thermal shutdown condition is indicated by the ERR signal going low.
APPLICATION INFORMATION Capacitor Selection
NONINVERTING WIDEBAND DRIVER
gm
ADP3331
GND
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature-proportional input offset voltage that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a virtual band gap voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources, which leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the band gap voltage to output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from the base current loading in conventional circuits is avoided. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitor. Most LDOs place strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of the load capacitance and resistance. Moreover, the ESR value required to keep conventional LDOs stable changes, depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. The ADP3331 solves this problem. It can be used with any good quality capacitor, with no constraint on the minimum ESR. The
Output Capacitor: The stability and transient response of the LDO is a function of the output capacitor. The ADP3331 is stable with a wide range of capacitor values, types, and ESR (anyCAP). A capacitor as low as 0.47 mF is all that is needed for stability; larger capacitors can be used if high current surges on the output are anticipated. The ADP3331 is stable with extremely low ESR capacitors (ESR 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types falls below the minimum over temperature or with dc voltage. Input Capacitor: An input bypass capacitor is not strictly required but is recommended in any application involving long input wires or high source impedance. Connecting a 0.47 mF capacitor from the input to ground reduces the circuit's sensitivity to PC board layout and input transients. If a larger output capacitor is necessary, a larger value input capacitor is also recommended. Noise Reduction Capacitor: A noise reduction capacitor can be used to reduce the output noise by 6 dB to 10 dB. This capacitor limits the noise gain when connected between the feedback pin (FB) and the output pin (OUT), as shown in Figure 3. Low leakage capacitors in the 10 pF to 500 pF range provide the best performance. Since FB is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible; long PC board traces are not recommended. When adding a noise reduction capacitor, use the following guidelines: Maintain a minimum load current of 1 mA when not in shutdown. For CNR values greater than 500 pF, add a 100 kW series resistor (RNR). It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values greater than 1 nF, this delay may be on the order of several milliseconds.
-6-
REV. A
ADP3331
ERR EOUT R4 RNR CNR VOUT +C2 0.47 F
ADP3331
OUT VIN C1 + 0.47 F IN SD FB GND R3
R1
Note that at output voltages above 5.2 V and below 1.6 V, nonstandard resistor values or the addition of a resistor to the divider network is required to achieve the best performance. For output voltages below 1.6 V, select a standard resistance value for R2 and then calculate the value of R1:
R2
ON OFF
EV R1 = A OUT - 1 R2 E VFB
(5)
Figure 3. Noise Reduction Circuit
Output Voltage
For output voltages above 5.2 V, select a standard resistance for R1, and calculate the value of R2:
E VFB R2 = R1 A VOUT - VFB E
(6)
The ADP3331 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2, and then fed back to the FB pin. Refer to Figure 3. For the output voltage to have the lowest possible sensitivity to temperature variations, it is important that the parallel resistance of R1 and R2 be as close as possible to 230 kW:
After selecting values for R1 and R2, calculate the value of R3 needed to maintain the 230 k impedance:
E R1 R2 R3 = 230 kW - A E R1 + R2
(7)
R1 R2 = 230 kW R1 + R2
(1)
Also, for the best accuracy over temperature, the feedback voltage should set for 1.204 V:
VOUT E R2 A = VFB E R1 + R2
(2)
Using standard values, as shown in Table I, will sacrifice some output voltage accuracy.
Output Current Limit
The ADP3331 is short-circuit protected by limiting the pass transistor's base drive current. The maximum output current is limited to about 300 mA.
Thermal Overload Protection
Where VOUT is the desired output voltage and VFB is the virtual band gap voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. Combining the above equations and solving for R1 and R2 results in the following formulas:
EV R1 = 230 A OUT kW E VFB
230 R2 = kW E V 1 - FB AV E OUT
(3)
The ADP3331 is protected by its thermal overload protection circuit against damage due to excessive power dissipation. Thermal protection limits the die temperature to a maximum of 165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where the die temperature starts to rise above 165C, the output current will be reduced until the die temperature has dropped to a safe level. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, the device's power dissipation should be externally limited so that the junction temperature will not exceed 125C.
Chip-on-Lead
(4)
The output voltage can be adjusted to any voltage from 1.5 V to 11.75 V. For example, Table I shows some representative feedback resistor values for output voltages in the specified range.
Table I. Feedback Resistor Selection
VOUT (V) 1.5 1.8 2.2 2.7 3.3 5 9
R1 (1%) 243 kW 340 kW 422 kW 511 kW 634 kW 953 kW 1.00 MW
R2 (1%) 1.00 MW 698 kW 511 kW 412 kW 365 kW 301 kW 154 kW
R3 (1%) 34.8 kW
The ADP3331 uses a patented Chip-on-Lead package design to ensure the best thermal performance in a SOT-23 footprint. In a standard SOT-23, most of the heat flows out of the ground pin. The Chip-on-Lead package uses an electrically isolated die attach, which allows all the pins to contribute to heat conduction. This technique reduces the thermal resistance to 190C/W on a 2-layer board compared to >230C/W for a standard SOT-23 lead frame. Figure 4 shows the difference between the standard SOT-23 and the Chip-on-Lead lead frames.
97.6 kW
REV. A
-7-
ADP3331
degree of overshoot is determined by several factors: the output voltage setting, the output load, the noise reduction capacitor, and the output capacitor.
SILICON DIE SILICON DIE WITH ELECTRICALLY ISOLATED DIE ATTACH NORMAL SOT-23-6 PACKAGE
The output voltage setting is determined by the application and cannot be tailored for minimum overshoot. In general, for output voltages of 2.2 V or less, the overshoot becomes larger as the output voltage decreases.
THERMALLY ENHANCED CHIP-ON-LEAD PACKAGE
Figure 4. Chip-on-Lead Package
Calculating Junction Temperature
Device power dissipation is calculated as follows: PD = (VIN - VOUT )I LOAD + (VIN )IGND
(8)
The output load is also determined by the system requirements. However, if the ADP3331 has no load on the output during startup, a small amount of preload can be added to minimize overshoot. A preload of 2 mA to 20 mA is recommended. A noise reduction capacitor, if not already being used, is suggested to reduce the overshoot. Values in the range of 10 pF to 100 pF work best, along with the preload suggested previously. The output capacitor can be adjusted to minimize the overshoot. Values in the 0.47 mF to 1.0 mF range should be used in conjunction with the preload and noise reduction capacitor. Further increases in the output capacitance may be acceptable if the output already has a sizable load during startup.
Higher Output Current
Where ILOAD and IGND are load current and ground current and VIN and VOUT are the input and output voltages, respectively. Assuming that the worst case operating conditions are ILOAD = 200 mA, IGND = 4 mA, VIN = 4.2 V, and VOUT = 3.0 V, the device power dissipation is PD = (4.2 V - 3.0 V ) 200 mA + (4.2 V ) 4 mA = 257 mW (9) The proprietary package used on the ADP3331 has a thermal resistance of 165C/W when placed on a 4-layer board and 190C/W when placed on a 2-layer board. This allows the ambient temperature to be significantly higher for a given power dissipation than with a standard package. Assuming a 4-layer board, the junction temperature rise above ambient will be approximately equal to D TJA = 0.257 W 165oC/W = 42.4oC To limit the junction temperature to 125C, the maximum allowable ambient temperature is
TA( MAX ) = + 125oC - 42.4oC = 82.6oC
Shutdown Mode (11) (10)
The ADP3331 can source up to 200 mA without any heat sink or pass transistor. If higher current is needed, an appropriate pass transistor can be used, as in Figure 5, to increase the output current to 1 A.
VIN = 3.3V C1 47 F MJE253* R1 50 VOUT = 1.8V @ 1A
IN
OUT C2 10 F FB 340k
ADP3331
SD GND *REQUIRES HEAT SINK
ERR
698k
Applying a TTL level high signal to the shutdown (SD) pin, or tying it to the input pin, will turn the output ON. Pulling the SD to 0.4 V or below, or tying it to ground, will turn the output OFF. In shutdown mode, the quiescent current is reduced to less than 1 mA.
Error Flag Dropout Detector
Figure 5. High Output Current Linear Regulator
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed circuit boards: 1. PC board traces with larger cross sectional areas will remove more heat from the ADP3331. For optimum heat transfer, specify thick copper and use wide traces. 2. The thermal resistance can be decreased by approximately 10% by adding a few square centimeters of copper area to the lands connected to the pins of the LDO. 3. The feedback pin is a high impedance input, and care should be taken when making a connection to this pin. The voltage setting resistors and noise reduction network must be located as close as possible. Long PC board traces are not recommended. Avoid routing traces near possible noise sources.
The ADP3331 will maintain its output voltage over a wide range of load, input voltage, and temperature conditions. If the output is about to lose regulation due to the input voltage approaching the dropout level, the error flag will be activated. The ERR output is an open collector, which will be driven low. Once set, the ERR flag's hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load.
Low Voltage Applications
In applications where the output voltage is 2.2 V or less, the ADP3331 may begin to exhibit some turn-on overshoot. The
-8-
REV. A
ADP3331
OUTLINE DIMENSIONS 6-Lead Small Outline Transistor Package [SOT-23] (RT-6)
Dimensions shown in millimeters
2.90 BSC
6
5
4
1.60 BSC
1 2 3
2.80 BSC
PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC
1.45 MAX
0.22 0.08 10 4 0 0.60 0.45 0.30
0.15 MAX
0.50 0.30
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AB
REV. A
-9-
ADP3331 Revision History
Location 5/03--Data Sheet changed from REV. 0 to REV. A. Page
Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to Output Voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
-10-
REV. A
-11-
-12-
C00146-0-5/03(A)

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